A conventional flip-flop is triggered either at the rising edge (or positive level) or the falling edge (negative level) of a clock cycle. The structure of the conventional rising edge trigger D-type flip-flop mainly consists of inverters and tri-state inverters. The basic circuit structure of a tri-state inverter is illustrated in FIG. 1. The operation of the tri-state inverter is described as follows: when the clock control signal CKP is logical "0" (the inverted clock control signal CKN is now logical "1"), the tri-state inverter is acted as an inverter; on the contrary, when the clock control signal CKP is logical "1" (the inverted clock control signal CKN is now logical "0"), the output Z of the tri-state inverter is floating (i.e., high impedance). Such a circuit is so-called a "tri-state inverter" due to the output thereof having three states, i.e., "0", "1" and "floating".
Referring to FIG. 2, it illustrates the circuit structure of a conventional rising edge trigger D-type flip-flop. The rising edge trigger D-type flip-flop consists of two tri-state inverters (20, 22), two latches (21, 23), clock control signal (CK) and inverted clock control signal (CKB). Latch (21) consists of two inverters (211, 212), wherein the output Z of the inverter (211) is connected to the input A of the inverter (212) and the output of the inverter (212) is connected to the input of the inverter (211). Such a connection forms a positive feedback circuit. Therefore, the value of the output N2 of the latch (21) can be maintained even if the input NI of the latch (21) is floating. The circuit structure of latch (23) is similar to that of latch (21).
The operation of the conventional rising edge trigger D-type flip-flop is described as follows: when the clock control signal CK is logical "0" (the inversed clock control signal CKB is now logical "1"), the tri-state inverter (20) is acted as an inverter and the other tri-state inverter (22) is floating ( i.e., the output N3 of the tri-state inverter (22) has a high impedance), therefore, the input D is inversed by tri-state inverter (20) and latched in latch 1 (21) but cannot be transmitted to latch 2 (23); when the clock control signal CK is changed from logical "0" to logical "1" (the inversed clock control signal CKB is now changed from logical "1" to logical "0"), the tri-state inverter (22) is acted as an inverter and the other tri-state inverter (20) is floating, therefore, the input D cannot be latched in latch 1 (21) and the data previously latched in latch 1 (21) is inversed by tri-state inverter (22) and latched in latch 2 (23) and finally transmitted to output Q of the flip-flop.
Therefore, the conventional rising edge D-type flip-flop is capable of performing one bit access during a clock cycle. However, the operation is merely performed at the rising edge of a clock and cannot be performed at the falling edge of the clock. Therefore, there is a need to overcome such an inefficient operation.